/* initiate PP DMA*/
/*Enable Parallel Port and PP DMA in same cycle*/
ustat4 = dm(PPCTL);
bit set ustat4 PPDEN|PPEN;
dm(PPCTL) = ustat4;
_main.end: jump(pc,0);
Listing 8-2. Parallel Port Status Driven Core Transfer
/* Register Definitions */
#define PPCTL
#define TXPP
#define RXPP
#define EIPP
#define EMPP
#define ECPP
/* Register Bit Definitions */
#define PPEN
#define PPDUR20
#define PPBHC
#define PPTRAN
#define PPBS
/* Source Buffer */
.section/dm seg_dmda;
.var source[8] = 0x11111111,
ADSP-2126x SHARC Processor Hardware Reference
0x1800
0x1808
0x1809
0x1810
0x1811
0x1812
0x00000001
0x00000026
0x00000040
0x00000200
0x00020000
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
Parallel Port
8-25
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