Chaining Dma Processes - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Once a program starts a DMA process, the process is influenced by two
external controls—DMA channel priority and DMA chaining. For more
information, see

"Chaining DMA Processes"

Chaining DMA Processes
The location of the DMA parameters for the next sequence comes from
the chain pointer (
ADSP-2126x processor automatically initializes and then begins another
DMA transfer when the current DMA transfer is complete. In addition to
the standard DMA parameter registers, each DMA channel (SP and SPI)
also has a register that points to the next set of DMA parameters stored
CP
in the processor's internal memory. In the SPI this is the
SPORT it is
CPSPxy
user initialized buffer in internal memory known as a transfer control
block (TCB). In TCB chain loading, the ADSP-2126x's IOP automati-
cally reads the TCB from internal memory and then loads the values into
the channel parameter registers to set up the next DMA sequence.
The structure of a TCB is conceptually the same as that of a traditional
linked-list. Each TCB has several data values and a pointer to the next
TCB. Further, the chain pointer of a TCB may point to itself to con-
stantly reiterate the same DMA.
A DMA sequence is defined as the sum of the DMA transfers for a single
channel, from when the parameter registers initialize to when the count
register decrements to zero. Each DMA channel has a chaining enable bit
( ) in the corresponding control register. This bit must be set to one to
CHEN
enable chaining. Chain pointer register should be cleared first before
enabling chaining. When chaining is enabled, DMA transfers are initiated
by writing a memory address to the
start a single DMA sequence, with no subsequent chained DMAs.
The register can be loaded at any time during the DMA sequence. This
CP
allows a DMA channel to have chaining disabled (
7-10
"Managing DMA Channel Priority" on page 7-18
below.
) register. In chained DMA operations, the
CP
. Each new set of parameters is stored in a four-word,
ADSP-2126x SHARC Processor Hardware Reference
register. This is also an easy way to
CP
CP
or
and in the
CPSPI
register address