Processing Element Registers; User-Defined Status Registers (Ustatx) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Core Registers
Table A-5. STKYx and STKYy Register Bit Descriptions (Cont'd)
Bit Name
24 SSEM
25 LSOV
26 LSEM
31–27 Reserved

User-Defined Status Registers (USTATx)

These are non-memory-mapped, universal, system registers (
). The reset value for these registers is 0x0000 0000. The
Sreg
isters are user-defined, general-purpose status registers. Programs can use
these 32-bit registers with bit-wise instructions (
ers). Often, programs use these registers for low overhead, general-purpose
flags or for temporary 32-bit storage of data.

Processing Element Registers

Except for the
data for each element's ALU, multiplier, and shifter. The inputs and out-
puts for processing element operations go through these registers. The
register lets programs transfer data between the data buses, but cannot be
an input or output in a calculation.
A-20
Description:  shows bits in both STKYx/y
 shows bits in STKYx only
Status Stack Empty. Indicates if the status stack is empty (if 1) or
not empty (if 0)—not sticky, cleared by a Push.
Loop Stack Overflow. Indicates if the loop counter stack and loop
stack are overflowed (if 1) or not overflowed (if 0)—sticky bit.
Loop Stack Empty. Indicates if the loop counter stack and loop
stack are empty (if 1) or not empty (if 0)—not sticky, cleared by a
Push.
register, the DSP's Processing Element registers store
PX
ADSP-2126x SHARC Processor Hardware Reference
and
Ureg
USTATx
, , , and oth-
SET CLEAR TEST



reg-
PX