Power Management Control Register (Pmctl - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

I/O Processor Registers

Power Management Control Register (PMCTL)

The Power Management Control register is a 32-bit memory-mapped reg-
ister. The
PMCTL
to control phase lock loop (PLL) multiplier and Divider (both input and
output) values, PLL bypass mode, and clock enabling control for peripher-
als (see Table A-22). This register also contains status bits, which keep
track of the status of the
The core can write to all bits except the read-only status bits. The
bit is a logical bit, that is, it can be set, but on reads it always responds
with zero.
PMCTL (0x2000)
TMRPDN
Timer Enable/Disable
SPIPDN
SPI Enable/Disable
SP3PDN
SP4–5 Enable/Disable
PLLBP
CLKOUTEN
Clockout Enable
DIVEN
PLL Divider Enable
Figure A-17. PMCTL Register
A-66
register's addresses is 0x2000. This register contains bits
CLK_CFG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
pins (read-only).
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1
0 0 0 0 0 0 0
DIVEN
0
CRAT
PL Clock Ratio
PPPDN
PP Enable/Disable
SP1PDN
SP0–1 Enable/Disable
SP2PDN
SP2–3 Enable/Disable
0
0
PLLM
PLL Multiplier
PLLD
Divide by 2, 4, 8, or 16
INDIV
Input Divider