I/O Processor - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

PM bus for transfers). Using the DM bus and PM bus in this way, with
one dedicated to each memory block, assures single-cycle execution with
two data transfers. In this case, the instruction must be available in the
cache. The processor also maintains single-cycle execution when one of
the data operands is transferred to or from off-chip, using the processor
parallel port.

I/O Processor

The ADSP-2126x Input/Output Processor (IOP) manages the SHARC
processor's off-chip data I/O to alleviate the core of this burden. Up to 22
simultaneous DMA transfers (22 DMA channels) are supported for trans-
fers between internal memory and serial ports (12), the input data port
(IDP) (8), SPI port (1), and the parallel port. The I/O processor can per-
form DMA transfers between the peripherals and internal memory at the
full core clock speed. The dual-ported architecture of the internal memory
allows the IOP and the core to access internal memory simultaneously
with no reduction in throughput.
Serial Ports. The ADSP-2126x processor features up to six synchronous
serial ports that provide an inexpensive interface to a wide variety of digi-
tal and mixed-signal peripheral devices. The serial ports can operate at up
to up to half of the processor core clock rate with maximum of 50M bits
per second. Each serial port features two data pins that function as a pair
based on the same serial clock and frame sync. Accordingly, each serial
port has two DMA channels and serial data buffers associated with it to
service the dual serial data pins. Programmable data direction provides
greater flexibility for serial communications. Serial port data can automat-
ically transfer to and from on-chip memory using DMA. Each of the serial
ports offers a TDM multichannel mode (up to 128 channels) and supports

-law or A-law companding. I
The serial ports can operate with least significant bit first (LSBF) or most
significant bit first (MSBF) transmission order, with word lengths from
three to 32 bits. The serial ports offer selectable synchronization and
ADSP-2126x SHARC Processor Hardware Reference
2
S support is also provided.
Introduction
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