Multifunction Computations - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

results in either
ter. With this arrangement, code can use the result registers as primary
and alternate accumulators, or code can use these registers as two parallel
accumulators. This feature facilitates complex math.
The register controls the access to alternate registers.
MODE1
page A-5 lists all the bits in
alternate registers (a 1 enables the alternate set):
• Secondary registers for computational unit results. Bit 2 (
• Secondary registers for hi register file,
Bit 7 (
SRRFH
• Secondary registers for lo register file,
Bit 10 (
The following example demonstrates how code should handle the maxi-
mum one cycle of latency—from the instruction that sets the bit in the
register to the point when the alternate registers may be accessed.
MODE1
Note that it is possible to use any instruction that does not access the
switching register file instead of using a
BIT SET MODE1 SRRFL;
NOP;
R0 = 7;

Multifunction Computations

The DSP supports multiple parallel (multifunction) computations by
using the many parallel data paths within its computational units. These
instructions complete in a single cycle, and they combine parallel opera-
tion of the multiplier and the ALU or dual ALU functions. The multiple
operations perform as if they were in corresponding single function
computations. Multifunction computations also handle flags in the same
ADSP-2126x SHARC Processor Hardware Reference
or , without regard to the state of the
MRF MRB
MODE1
)
)
SRRFL
/* activate alternate reg. file */
/* wait for access to alternates */
Processing Elements
. The following bits in
–
R8 R15
–
R0 R7
instruction.
NOP
regis-
MODE1
Table A-2 on
control
MODE1
)
SRCU
and – .
S8 S15
and – .
S0 S7
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