Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 765

Table A-40. PCG_CTLA_0 Register Bit Descriptions
Bits Name
19–0 FSADIV
29–20 FSAPHASE_HI
30 ENFSA
31 ENCLKA
PCG_CTLA_1 (0x24C1)
CLKASOURCE
Clock A Source
FSASOURCE
Frame Sync A Source
Figure A-57. PCG_CTLA_1 Register
ADSP-2126x SHARC Processor Hardware Reference
Description
Divisor for Frame Sync A.
Phase for Frame Sync A. Represents the upper half of the
20-bit value for the channel A frame sync phase. The phase
represents the number of input clocks remaining in the first
frame after the signal is enabled.
See FSAPHASE_LO (Bits 29-20) in PCG_CTLA_1 described
on on page
Enable Frame Sync A.
0 = Frame Sync A generation disabled
1 = Frame Sync A generation enabled
Enable Clock A.
0 = Clock A generation disabled
1 = Clock A generation enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
Registers Reference
A-144.
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
FSAPHASE_LO
Frame Sync A
Phase 9:0
CLKADIV
CLK A Divisor
A-143