Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 134

Hide thumbs Also See for ADSP-21261 SHARC:

Table of Contents

Table 3-7. System/Emulator Memory-Mapped Registers

3. Reading from all other memory-mapped registers and data-buffers

(for example

three cycles. Therefore, a total of four cycles is needed for that

instruction to complete.

4. If the following sequence of three instructions is executed without

any other instruction between them, then the processor stalls for

a. Instruction 1: Compute instruction affecting flags such as

R2 = R3 – R4;

b. Instruction 2: Conditional instruction involving post-mod-

ify addressing such as

c. Instruction 3: Instruction involving post-modify or

pre-modify addressing involving the same

R0 = DM(I1,M2);

ADSP-2126x SHARC Processor Hardware Reference

) stalls the processor core for

IF EQ DM(I1,M1) = R15;

Need help?

Do you have a question about the ADSP-21261 SHARC and is the answer not in the manual?