Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 818

Index
DMA
sequences, TCB loading,
setting up, 7-30
setting up on SPORT channels,
set up and initiate a chain,
set up and initiate a chain over SPI port,
7-14
SPI slave mode, 10-10, 10-11, 10-44,
10-45
start address See IISPI register
status See PPDS bit
switching from receive to transmit mode,
10-22, 10-52
switching from transmit to receive mode,
10-21, 10-50
transfer direction, 7-21
transfer error See SPIDMAC register
transfers, 11-18
transfers, starting, 11-18
transmit or receive operations (SPI),
10-46
word count See CSPI register
DMA channel
latency, 7-8
parameter registers, listed,
priority, 7-18
setting up, 7-30
DMA Internal Modifier Address (IMPP)
register, 8-16
DMA Internal Word Count (ICPP)
register, 8-16
DMA Start Internal Index Address (IIPP)
register, 8-16
DMx register, A-55, A-58
double register operations
unsupported, 2-52
DO UNTIL instruction,
See also loops, 3-26
I-8
(continued)
7-13
9-68
7-14
7-28
3-26
ADSP-2126x SHARC Processor Hardware Reference
DSP
architectural overview,
serial mode, 9-67
DSxEN(3-0) bits, 10-14, 10-36,
DSxEN bits, 10-36
DSxEN (SPI device select) bits,
DTYPE and data formatting
DSP serial mode, 9-41
multichannel, 9-42
DTYPE bit, 9-53, A-76
dual add and subtract,
dual-data accesses, 5-28
dual processing element moves (broadcast
load mode), 5-56
D unit See DAGs or ALU
DXS_B bit, A-78
DXS data status See DXS_x bit
DXS_x bit, 9-59
E
early vs. late frame syncs,
ECEPx registers, 7-25
ECPP register, 15-22, A-113
edge-related interrupts, four conditions,
12-30
edge-sensitive interrupts, 3-53, A-8,
EEMUENS bit, A-57
EEMUIN buffer, 6-4
EEMUINENS bit, A-57,
EEMUINFULLS bit, A-57,
EEMUOUIRQENS bit,
EEMUOUT FIFO buffer,
EEMUOUTRDY bit,
EEMUSTAT register, 6-4,
effect latency See also latency,
E field, address, A-33
EIPP register, 7-25, 8-17,
EIPPx registers, 15-22
EMEPx registers, 7-25
EMISO bit, 10-36
1-5
A-95
10-45
2-43
9-37
G-4
A-61
A-60
A-60
6-4
A-60
6-8
3-63
A-112