Moving Data Between SPORTS and Internal Memory
Table 9-10. SPORT DMA Parameter Registers Addresses (Cont'd)
Register
CPSP4A
IISP4B
IMSP4B
CSP4B
CPSP4B
IISP5A
IMSP5A
CSP5A
CPSP5A
IISP5B
IMSP5B
CSP5B
CPSP5B
Reserved (0x850 to 0x85F)
When programming a serial port channel (either A or B) as a transmitter,
only the corresponding
while the receive buffers (
when the SPORT channel A and B is programmed as a receiver, only the
corresponding
When performing core-driven transfers, write to the buffer designated by
the
bit setting in the
SPTRAN
the serial port logic performs the data transfer from internal memory
to/from the appropriate buffer depending on the
inactive SPORT data buffers are read or written to by core while the port
is being enabled, the core will hang. For example, if a SPORT is pro-
grammed to be a transmitter, while at the same time the core reads from
the receive buffer of the same SPORT, the core hangs just as it would if it
9-72
Address
DMA Channel
0x843
8
0x844
9
0x845
9
0x846
9
0x847
9
0x848
10
0x849
10
0x84A
10
0x84B
10
0x84C
11
0x84D
11
0x84E
11
0x84F
11
and
TXSPxA
RXSPxA
and
RXSP0A
RXSP0B
SPCTLx
ADSP-2126x SHARC Processor Hardware Reference
SPORT Buffer
RXSP4A or TXSP4A
RXSP4B or TXSP4B
RXSP4B or TXSP4B
RXSP4B or TXSP4B
RXSP4B or TXSP4B
RXSP5A or TXSP5A
RXSP5A or TXSP5A
RXSP5A or TXSP5A
RXSP5A or TXSP5A
RXSP5B or TXSP5B
RXSP5B or TXSP5B
RXSP5B or TXSP5B
RXSP5B or TXSP5B
SPORT buffer becomes active,
TXSPxB
and
) remain inactive. Similarly,
RXSPxB
SPORT buffer is activated.
register. For DMA-driven transfers,
SPTRAN
bit setting. If the
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