Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 732

I/O Processor Registers
Table A-33. Parallel Port Register (PPCTL) Bit Definitions
Bit Name
0 PPEN
5–1 PPDUR
6 PPBHC
7 PP16
8 PPDEN
9 PPTRAN
A-110
Definition
Parallel Port Enable. Enables if set, (= 1) or disables if
cleared, (= 0) the parallel port. Clearing this bit clears
FIFO and status. If an
RD
started, it completes normally before the port is disabled.
The parallel port is ready to transmit or receive 2 cycles
after enabling. An ALE cycle always occurs before the first
read or write cycle after PPEN is enabled.
Parallel Port Duration. The duration of Parallel Port data
cycles is based on core-clock and controlled by these five
bits as follows:
00000 = Reserved
00001 = Reserved
00010 = 2 Wait States = 3 Core Clock Cycles;
66 MHz throughput
00011 = 3 Wait States = 4 Core Clock Cycles;
50 MHz throughput
00100 = 4 Wait States = 5 Core Clock Cycles;
40 MHz throughput
00101 = 5 Wait States = 6 Core Clock Cycles;
33 MHz throughput
...
11111 = 31 wait states; 6.25MHz throughput
Bus Hold Cycle. Inserts a bus hold cycle at the end of
every access (read or write cycle) if set, (= 1) or no bus
hold cycle occurs if cleared, (= 0). During a BHC address
and/or data continue to be driven for one cycle.
Parallel Port External Data Width. Selects the external
data width to 16 bits if set, (= 1) or 8 bits if cleared, (= 0).
Parallel Port DMA Enable. Enables if set, (= 1) DMA on
the parallel port or disables DMA if cleared, (= 0). When
PPDEN is cleared, any DMA requests already in the pipe-
line complete, and no new DMA requests are made. This
does not affect FIFO status.
Parallel Port Transmit/Receive Select. Indicates if the
processor is reading from external memory if cleared, (= 0)
or writing to external memory if set, (= 1).
ADSP-2126x SHARC Processor Hardware Reference
, , or ALE cycle has already
WR
Default
0
Bit 1 = 1
Bit 2=1
Bit 3=1
Bit 4=0
Bit 5=1
1
0
0
0