Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 693

SPCTL0 (0xc00)
SPCTL1 (0xc01)
SPCTL2 (0x400)
SPCTL3 (0x401)
SPCTL4 (0x800)
SPCTL5 (0x801)
(Bits 15–0)
DIFS
Data Independent TX FS
(if SPTRAN=1 or RX FS (if
SPTRAN=0)
1=Data Independent
0=Data Dependent
IFS
Internally-generated FS
1=Internal
0=External
FSR
Frame Sync Requirement
1=Frame Sync Required
0=Frame Sync Not Required
CKRE
Clock Edge for Data Frame Sync
Sampling or Driving
1=Rising Edge
0=Falling Edge
OP MODE
SPORT Operation Mode
0=DSP Serial Mode/Multichannel Mode
(This bit must be set to 0)
Figure A-19. SPCTLx Control Bits for Standard DSP Serial Mode (Lower)
ADSP-2126x SHARC Processor Hardware Reference
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
Registers Reference
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
SPEN_A
SPORT Enable A
1=Enable
0=Disable
DTYPE
Data Type
00=Right-justify
01=Right-justify, sign extend
SPIMS
10=Compand µ-law
11=Compand A-law
LSBF
Least Significant Bit Format
1=LSB first
0=MSB first
SLEN
Serial Word Length=1
PACK
16/32 Packing
1=Packing
0=No Packing
ICLK
Internally Generated
SPORTx_CLK
1=Internal Clock
0=External Clock
A-71