Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 7

Loops and Sequencing ................................................................. 3-25
Restrictions on Ending Loops ................................................ 3-27
Restrictions on Short Loops ................................................... 3-28
Loop Address Stack ............................................................... 3-31
Loop Counter Stack .............................................................. 3-32
Reading From LCNTR in a LOOP .................................... 3-36
SIMD Mode and Sequencing ...................................................... 3-36
Conditional Compute Operations .......................................... 3-38
Conditional Branches and Loops ........................................... 3-38
Conditional Data Moves ........................................................ 3-38
Case #1: Complementary Register Pair Data Move ............. 3-39
Example 1: Register-to-Memory Move - PEx Explicit Register
3-39
Example 2: Register Move - PEy Explicit Register .......... 3-40
Example 3: Register-to-Memory Move - PEx Explicit Register
3-40
Example 4: Register-to-Memory Move - PEy Explicit Register
3-41
Case #2: Uncomplimentary-to-Complementary Register Move 3-42
Example: Register Moves - Uncomplimentary-to-Complementary
3-42
Case #3: Complementary-to-Uncomplimentary Register Move 3-43
Example: Register Moves - Complementary-to-Uncomplimentary
3-43
ADSP-2126x SHARC Processor Hardware Reference
Contents
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