Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 417

Table 9-8. Serial Port DMA Channels
Channel Data Buffer
0 RXSP1A/TXSP1A
1 RXSP1B/TXSP1B
2 RXSP0A/TXSP0A
3 RXSP0B/TXSP0B
4 RXSP3A/TXSP3A
5 RXSP3B/TXSP3B
6 RXSP2A/TXSP2A
7 RXSP2B/TXSP2B
8 RXSP5A/TXSP5A
9 RXSP5B/TXSP5B
10 RXSP4A/TXSP4A
11 RXSP4B/TXSP4B
Data-direction programmability is supported in Standard DSP Standard
Serial, Left-justified Sample Pair, and I
bit in (0 =
SPCTLx
register for the SPORT becomes active.
The SPORT DMA channels are assigned higher priority than all other
DMA channels (for example, the SPI port and the parallel port) because of
their relatively low service rate and their inability to hold off incoming
data. Having higher priority causes the SPORT DMA transfers to be per-
formed first when multiple DMA requests occur in the same cycle.
Although the DMA transfers are performed with 32-bit words, serial ports
can handle word sizes from 3 to 32 bits, with 8 to 32 bits for I
serial words are 16 bits or smaller, they can be packed into 32-bit words
for each DMA transfer. DMA transfers are configured using the
in the Control registers. When serial port data packing is enabled
SPCTLx
ADSP-2126x SHARC Processor Hardware Reference
Description
SPORT1 A data
SPORT1 B data
SPORT0 A data
SPORT0 B data
SPORT3 A data
SPORT3 B data
SPORT2 A data
SPORT2 B data
SPORT5 A data
SPORT5 B data
SPORT4 A data
SPORT4 B data
, 1 = ) determines whether the receive or transmit
RX TX
Priority
Highest
Lowest
2
S modes. The value of the
Serial Ports
SPTRAN
2
S mode. If
bit
PACK
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