Master Mode Dma Transfers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

4. The reception or transmission continues until
until the slave has received the proper number of clock cycles.
5. The slave device continues to receive or transmit with each new
falling-edge transition on
If the transmit buffer remains empty, or the receive buffer remains full,
the devices operate according to the states of the
registers.
SPICTLx
• If
SENDZ
transmits zero's on the
• If
SENDZ
mits the last word transmitted before the transmit buffer became
empty.
• If = 1 and the receive buffer is full, the device continues to
GM
receive new data from the
the
RXSPI
• If = 0 and the receive buffer is full, the incoming data is dis-
GM
carded, and the

Master Mode DMA Transfers

To configure the SPI port for master mode DMA transfers:
1. Specify which
one or more of the
registers.
2. Enable the device as a master and configure the SPI system by
selecting the appropriate word length, transfer format, baud rate,
and so on in the
(bits 1–0) in the
or receive with DMA mode (
ADSP-2126x SHARC Processor Hardware Reference
SPIDS
= 1 and the transmit buffer is empty, the device repeatedly
MISO
= 0 and the transmit buffer is empty, it repeatedly trans-
MOSI
buffer.
registers are not updated.
RXSPIx
pins to use as the slave-select signals by setting
FLAG
bits (bits 3–0) in the SPI flag (
DSxEN
SPIBAUDx
registers is configured to select transmit
SPICTLx
Serial Peripheral Interface Port
or active
SPICLK
SENDZ
pin.
pin, overwriting the older data in
and registers. The
SPICTLx
= 10).
TIMOD
is released or
SPIDS
clock edge.
and bits in the
GM
)
SPIFLGx
field
TIMOD
10-45