Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 666

Core Registers
SYSCTL (0x30024)
Reserved
PPFLGS
Parallel Port Mode Enable
1=Enable
0=Disable Parallel Port. ADDR pins are FLAGS
(permits core writes)
TMREXPEN
Flag3 Mode
1=FLAG3 is in TIMEXP mode
0=FLAG3 is in FLAG3 mode (permits core writes)
IRQ2EN
Flag2 Mode
1=FLAG2 is in IRQ2 mode
0=FLAG2 is in FLAG2 mode (permits core writes)
Reserved
IMDW1
Internal Memory Block 1 Data Width
1=Data bus width is 48 bits
0=Data bus is 32 bits
IMDW0
Internal Memory Block 0 Data Width
1=Data bus width is 48 bits
0=Data bus is 32 bits
Reserved
DCPR
Priority Bit Enable
1=Rotating priority
0=Fixed priority (permits core writes)
Figure A-13. SYSCTL Register
A-44
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
IRQ0EN
Flag0 Mode
1=FLAG0 is in IRQ0 mode
0=FLAG0 is in FLAG0 mode
(permits core writes)
IRQ1EN
Flag1 Mode
1=FLAG1 is in IRQ1 mode
0=FLAG1 is in FLAG1 mode
(permits core writes)
SRST
Software Reset
1=Disable
0=Enable (permits core writes)
Reserved
IIVT
Internal Interrupt Vector Table
1=Interrupt Vector Table is in
internal RAM
0=Interrupt Vector Table is not
in internal RAM
(permits core reads)
Reserved