Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 674

Core Registers
Table A-17. Emulation Control Register (EMUCTL) Definitions (Cont'd)
Bit # Name
9 NEGDA1
10 NEGDA2
11 NEGIA1
12 NEGIA2
13 NEGIA3
14 NEGIA4
15 NEGIO1
16 NEGEP1
17 ENBPA
18 ENBDA
19 ENBIA
20–21 Reserved
A-52
Function
Negate data memory address breakpoint #1 see NEGPA1 bit
description.
Negate data memory address breakpoint #2 see NEGPA1 bit
description.
Negate instruction address breakpoint #1 see NEGPA1 bit
description.
Negate instruction address breakpoint #2. see NEGPA1 bit
description.
Negate instruction address breakpoint #3 see NEGPA1 bit
description.
Negate instruction address breakpoint #4 see NEGPA1 bit
description.
Negate I/O address breakpoint see NEGPA1 bit description.
Negate EP address breakpoint see NEGPA1 bit description.
Enable program memory data address breakpoints. Enable each
breakpoint group. Note that when the ANDBKP bit is set, break-
point types not involved in the generation of the effective break-
point must be disabled. (0 = disable breakpoints, 1 = enable
breakpoints)
Enable data memory address breakpoints see ENBPA bit descrip-
tion.
Enable instruction address breakpoints see ENBPA bit descrip-
tion.
ADSP-2126x SHARC Processor Hardware Reference