Precision Clock Generator - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

13 PRECISION CLOCK
GENERATOR
The Precision Clock Generator (PCG) consists of two units, each of
which generates a pair of signals derived from a clock input signal. The
pair of units, A and B, are identical in functionality and operate inde-
pendently of each other. Each unit generates two signals that are normally
used as a clock frame sync pair. The unit that generates the clock is rela-
tively simple, since digital clock signals are usually regular and
symmetrical. The unit that generates the frame sync output, however, is
designed to be extremely flexible and capable of generating the wide vari-
ety of framing signals needed by the many types of peripherals that can be
connected to the signal routing unit (SRU).
"Signal Routing Unit" on page 12-3.
The core phase locked loop (PLL) has been designed to provide clocking
for the processor core. Although the performance specifications of this
PLL are appropriate for the core, they have not been optimized or speci-
fied for precision data converters where jitter directly translates into time
quantization errors and distortion.
The PCG can accept its clock input either directly from the external oscil-
lator (or discrete crystal) connected to the
the 20 DAI pins. This allows a design to contain an external clock with
performance specifications appropriate for the application target.
ADSP-2126x SHARC Processor Hardware Reference
For more information, see
/ pins or from any of
CLKIN XTAL
13-1