Current Loop Counter Register (Curlcntr; Loop Counter Register (Lcntr; Timer Period Register (Tperiod - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Core Registers
Table A-11. LADDR Register Bit Descriptions
Bits Value
23–0 Loop Termination Address
28–24 Termination Code
29 Reserved (always reads zero)
31–30 Loop Type Code
00 = arithmetic condition-based (not LCE)
01 = counter-based, length 1
10 = counter-based, length 2
11 = counter-based, length > 2

Current Loop Counter Register (CURLCNTR)

The
CURLCNTR
only). The Current Loop Counter register provides access to the loop
counter stack and tracks iterations for the
cuted. For more information on how to use the
"Loop Counter Stack" on page

Loop Counter Register (LCNTR)

The register is a non-memory-mapped, universal register (
LCNTR
only). The Loop Counter register provides access to the loop counter stack
and holds the count value before the
more information on how to use the
Stack" on page

Timer Period Register (TPERIOD)

The register is a non memory-mapped, universal register (
TPERIOD
only). The Timer Period register contains the decrementing timer count
value, counting down the cycles between timer interrupts. For more infor-
mation on how to use the
on page 3-46.
A-36
register is a non-memory-mapped, universal register (
3-32.
3-32.
TPERIOD
ADSP-2126x SHARC Processor Hardware Reference
DO UNTIL LCE
CURLCNTR
loop is executed. For
DO UNTIL LCE
register, see
LCNTR
register, see "Timer and Sequencing"
Ureg
loop being exe-
register, see
Ureg
"Loop Counter
Ureg