Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 335

access constraints (occurrence of
of data cycles, and/or addition of hold time cycles).
The maximum parallel port speed is 1/3 of the core. The relationship
between core clock and parallel port speed is static. For a 200 MHz core
clock, the parallel port runs at 66 MHz. Since there is no parallel port
clock signal, it is easiest to think of parallel port throughput in terms of
core clock cycles.
As described in
accesses require both
tional data cycles to transmit or receive data. Therefore, the throughput
on the parallel port is determined by the duration and number of these
cycles per word. The duration of each type of cycle is shown below and the
frequency is determined by the external memory width.

There is one case where the frequency is also determined by the
external address modifier register (
• cycles are fixed at 3 core cycles (
ALE
the
PPDUR
clock cycles. Address for
goes HIGH (active) and remains on bus a half cycle after
ALE
goes LOW (inactive). Therefore, the total
1/2 + 2 + 1/2 = 3 core clock cycles. Please refer to the data sheet for
more precise timing characteristics.
• Data cycle duration is programmable with a range of 3 to 32
cycles. They may range from 4 to 33 cycles if the
The following sections show examples of transfers that demonstrate the
expected throughput for a given set of parameters. Each word transfer
sequence is made up of a number of data cycles and potentially one addi-
tional cycle.
ALE
ADSP-2126x SHARC Processor Hardware Reference
ALE
"Parallel Port Operation" on page
cycles to latch the external address and addi-
ALE
or bit settings. In this case, the
BHC
ALE
cycles at page boundaries, duration
8-5, parallel port
).
EMPP
) and are not affected by
CCLK
ALE
is set up a half core clock cycle before
cycles on the bus are
ALE
Parallel Port
is high for 2 core
ALE
CCLK
bit is set (=1).
BHC
8-13