Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 402

SPORT Control Registers and Data Buffers
Table 9-6. SPCTLx Control Bit Comparison in Four SPORT Operation
Modes (Cont'd)
Standard DSP
Bit Serial Mode
12 CKRE
13 FSR
14 IFS
15 DIFS
16 LFS
17 LAFS
18 SDEN_A
19 SCHEN_A
20 SDEN_B
21 SCHEN_B
22 FS_BOTH
23 BHD
24 SPEN_B
25 SPTRAN
26 ROVF_B, or
TUVF_B
27 DXS_B
28 DXS_B
29 ROVF_A, or
TUVF_A
30 DXS_A
31 DXS_A
9-52
2
Left-justified and I S
Sample Pair Mode
Reserved
Reserved
Reserved
DIFS
FRFS
LAFS
SDEN_A
SCHEN_A
SDEN_B
SCHEN_B
Reserved
BHD
SPEN_B
SPTRAN
ROVF_B, or TUVF_B TUVF_B
DXS_B
DXS_B
ROVF_A, or TUVF_A TUVF_A
DXS_A
DXS_A
ADSP-2126x SHARC Processor Hardware Reference
Multichannel Mode
Transmit Control Bits
(SPORT0, 2,
and 4)
CKRE
Reserved
Reserved
Reserved
LTDV
Reserved
SDEN_A
SCHEN_A
SDEN_B
SCHEN_B
Reserved
BHD
Reserved
Reserved
TXS_B
TXS_B
TXS_A
TXS_A
Receive Control
Bits (SPORT1, 3,
and 5)
CKRE
Reserved
IMFS
Reserved
LRFS
Reserved
SDEN_A
SCHEN_A
SDEN_B
SCHEN_B
Reserved
BHD
Reserved
Reserved
ROVF_B
RXS_B
RXS_B
ROVF_A
RXS_A
RXS_A