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CBUFEN
Circular Buffer Addressing Enable
BDCST1
Broadcast Register Loads
BDCST9
Broadcast Register Loads
TRUNC
Truncation Rounding Mode
Select
SSE
Fixed-Point Sign Extension
Select
ALUSAT
ALU Saturation Select
IRPTEN
Global Interrupt Enable
NESTM
Nesting Multiple Interrupts Enable
SRRFL
Secondary Registers Register
File Low Enable
SRRFH
Secondary Registers Register
File High Enable
Figure A-3. MMASK Register Bits
A-10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
15 14 13 12 11 10
9
0
0
0
0
0
0
0
ADSP-2126x SHARC Processor Hardware Reference
0
0
0
0
1
0
0
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
RND32
Rounding For 32-Bit
Floating-Point Data Select
PEYEN
Processor Element Y Enable
1
0
0
0
BR8
Bit-Reverse Addressing for I8
BR0
Bit Reverse Addressing for I0
SRCU
Secondary Registers
Computational Units Enable
SRD1H
Secondary Registers DAG1 High
Enable
SRD1L
Secondary Registers DAG1 Low
Enable
SRD2H
Secondary Registers DAG2 High
Enable
SRD2L
Secondary Registers DAG2 Low
Enable
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