Master Mode Dma Operation - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPI Data Transfer Operations

Master Mode DMA Operation

To configure the SPI port for Master mode DMA transfers:
1. Specify which
ting one or more of the SPI Flag (
bits 3–0).
2. Enable the device as a master and configure the SPI system by
selecting the appropriate word length, transfer format, baud rate,
and so on in the
1–0) in the
receive with DMA mode (
3. Activate the desired slaves by clearing one or more of the SPI flag
bits (
SPIFLGx
4. For a single DMA, define the parameters of the DMA transfer by
writing to the
write the chain pointer address to the
register is a 20-bit read-write register that can contain address
information.
5. Write to the SPI DMA configuration register, (
the DMA direction (
engine (
SPICHEN

To avoid data corruption, enable the SPI port before enabling
DMA.
If flags are used as slave selects, programs should activate the flags by clear-
ing the flag after
the DMA. When
must use automatic flags using
10-14
pin(s) to use as the slave-select signal(s) by set-
FLG
and
SPIBAUD
register is configured to select transmit or
SPICTL
) of if
SPIFLG
,
IISPI IMSPI
SPIRCV
, bit 0). If DMA chaining is desired, set (= 1) the
SPIDEN
bit (bit 4) in the
SPIDMAC
and
SPICTL SPIBAUD
= 0, and a program is using DMA, the program
CPHASE
SPIFLGx
ADSP-2126x SHARC Processor Hardware Reference
register) Select bits (
SPIFLG
registers. The
SPICTL
= 10).
TIMOD
= 1.
CPHASE
, and registers. For DMA chaining,
CSPI
CPSPI
, bit 1) and to enable the SPI DMA
register.
are configured, but before enabling
.
DSxEN
field (bits
TIMOD
register. The
CPSPI
), to specify
SPIDMAC