Group F - Pin Enable Signals - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Group F – Pin Enable Signals
Group F signals, shown in
DAI pin is used as an output or an input by setting the source for the pin
buffer enables. When a pin buffer enable (
signal present at the corresponding pin buffer input (
off-chip as an output. When a pin buffer enable is cleared (= 0) the signal
present at the corresponding pin buffer input is ignored.
The Pin Enable Control registers activate the drive buffer for each of the
20 DAI pins. When the pins are not enabled (driven), they can be used as
inputs.
Table 12-7. Group F Sources – Pin Output Enable
Signal Inputs
DAI Pin Register
SRU_PBEN0
SRU_PBEN1
SRU_PBEN2
SRU_PBEN3
ADSP-2126x SHARC Processor Hardware Reference
Table 12-7, are used to specify whether each
Signal Sources
Bit field
• 2 Pin Enable Logic Level (High/Low) Options
DAI_PB01_I
• 6 Miscellaneous A Control Pins
DAI_PB02_I
(MISCAx_O)
DAI_PB03_I
• 24 Pin Enable Options for 6 Serial Ports (one each for
DAI_PB04_I
FS, Data Channel A/B, and Clock) (SPORTx_-
DAI_PB05_I
CLK_PBEN_O), (SPORTx_FS_PBEN_O),
DAI_PB06_I
(SPORTx_DA_PBEN_O),
DAI_PB07_I
(SPORTx_DB_PBEN_O)
DAI_PB08_I
• 3 Timer Pin Enables (TIMERx_PBEN_O)
DAI_PB09_I
• 6 Flags Pin Enables (FLGxx_PBEN_O)
DAI_PB10_I
DAI_PB11_I
DAI_PB12_I
DAI_PB13_I
DAI_PB14_I
DAI_PB15_I
DAI_PB16_I
DAI_PB17_I
DAI_PB18_I
DAI_PB19_I
DAI_PB20_I
Digital Audio Interface
) is set (= 1) the
DAI_PBENxx_I
DAI_PBxx_I
) is driven
12-25