Long Word Addressing Of Dual-Data - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Internal Memory Access Listings

Long Word Addressing of Dual-Data

Figure 5-22 shows the SISD, dual-data, long word addressed access mode.
For long word addressing, the processor treats each data bus as a 64-bit
long word lane. The 64-bit values for the long word accesses completes a
transfer using the full width of the PM or DM data bus.
In Figure 5-22, the access targets
This instruction accesses
targets registers
and in . The processor zero-fills the least significant 8 bits of all the
RB PEx
registers.
Programs must be careful not to explicitly target neighbor registers in this
instruction. While the syntax lets programs target these registers, one of
the explicit accesses targets the implicit target of the other access. The pro-
cessor resolves this conflict by performing only the access with higher
priority. For more information on the priority order of data register file
accesses, see "Data Register File" on page

SIMD mode operation is only supported in NW and SW space.
5-54
PEx
WORD X0
and and implicitly targets their neighbor registers
RX RA
ADSP-2126x SHARC Processor Hardware Reference
registers in SISD mode operation.
and with syntax that explicitly
WORD Y0
2-38.
RY