Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 100

Multifunction Computations
way as the single function computations, except that in the dual add/sub-
tract computation, the ALU flags from the two operations are ORed
together.
To work with the available data paths, the computational units constrain
which data registers hold the four input operands for multifunction com-
putations. These constraints limit which registers may hold the X input
and Y input for the ALU and multiplier.
Figure 2-15 shows a computational unit and indicates which registers may
serve as X inputs and Y inputs for the ALU and multiplier. For example,
the X input to the ALU can only be
shifter is gray in
operations.
Table 2-11, Table
tion computations. For more information on assembly language syntax,
see SHARC Processor Programming Reference. In these tables, note the
meaning of the following symbols:
• , ,
Rm Ra Rs
• , ,
Fm Fa Fs
• indicates data file registers
R3–0
cates data file registers
• indicates data file registers
R7–4
cates data file registers
• indicates data file registers
R11–8
indicates data file registers
•
R15–12
indicates data file registers
2-42
Figure 2-15 to indicate no shifter multifunction
2-12, Table 2-13, and
, , indicate any register file location; fixed-point
Rx Ry
, , indicate any register file location; floating-point
Fx Fy
,
F3
,
F7
indicates data file registers
ADSP-2126x SHARC Processor Hardware Reference
, , or
R8 R9 R10 R11
Table 2-14
, , , or
R3 R2 R1
, , or
F2 F1 F0
, , , or
R7 R6 R5
, , or
F6 F5 F4
, ,
R11 R10 R9
, , , or
F11 F10 F9 F8
, ,
R15 R14 R13
, , , or
F15 F14 F13 F12
. Note that the
list the multifunc-
, and indi-
R0 F3–0
, and indi-
R4 F7–4
, or , and
R8 F11–8
, or , and
R12 F15–12