Stacking Status During Interrupts - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Interrupts and Sequencing
registers. Table A-5 on page A-18
routines for arithmetic interrupts must clear the appropriate
bits to clear the interrupt. If the bits are not cleared, the interrupt is
STKYy
still active after the return from interrupt (

Status bits in
tion, see "SIMD (Computational) Operations" on page 2-50.
One event can cause multiple interrupts. The timer decrementing to zero
causes two timer expired interrupts to be latched,
and (low priority). This feature allows selection of the priority for
TMZLI
the timer interrupt. Programs should unmask the timer interrupt with the
desired priority and leave the other one masked. If both interrupts are
unmasked, the DSP services the higher priority interrupt first, then it ser-
vices the lower priority interrupt.
The register also supports software interrupts. When a program sets
IRPTL
the latch bit for one of these interrupts (
the sequencer services the interrupt, and the DSP branches to the corre-
sponding interrupt routine. Software interrupts have the same behavior as
all other maskable interrupts.

Stacking Status During Interrupts

In an interrupt driven system, the DSP must be restored to its pre-inter-
rupt state after an interrupt is serviced. The sequencer's status stack eases
the return from an interrupt by eliminating some interrupt service over-
head—register saves and restores.
The status stack is fifteen locations deep. The stack is full when all entries
are occupied, is empty when no entries are occupied, and is overflowed if a
3-56
lists the bits in these registers. Service
apply only in SIMD mode.
STKYy
ADSP-2126x SHARC Processor Hardware Reference
).
RTI
For more informa-
(high priority)
TMZHI
, ,
SFT0I SFT1I SFT2I
or
STKYx
, or ),
SFT3I