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IOP/Core Interaction Options
The
PCI
Also, interrupt requests enabled by the
the
IMASK
Because the
PCI
register, programs must use care when writing and reading addresses to
and from the register. To prevent errors, programs should mask out the
bit (bit 19) when copying the address in a chain pointer to another
PCI
address register.
The DMA registers are shown in
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
IIx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
IMx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Cx
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
EIPP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
EMPP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ECPP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
CPx
Figure 7-2. DMA Parameter Registers
7-12
bit only effects DMA channels that have chaining enabled.
register.
bit is not part of the memory address in the chain pointer
Figure
PCI BIT
PROGRAM – CONTROLLED INTERRUPT BIT
IF THIS BIT IS SET, THE I/O PROCESSOR WILL GENERATE A
DMA INTERRUPT AFTER EVERY DMA IN THE CHAIN.
ADSP-2126x SHARC Processor Hardware Reference
bit are maskable with
PCI
7-2.
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0
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0
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