Channel Selection Registers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPORT Operation Modes
The ,
SPCTL0 SPCTL2
Status (sticky, read-only) bit indicates (if set, =1) if the multichannel
signal (from internal or external source) occurred while the
SPORTx_FS
buffer was empty. The SPORTs transmit data whenever they detect a
signal. If cleared (=0), no
SPORTx_FS

This bit applies to multichannel mode only when the SPORTs are
configured as transmitters.
Bits 31-30 (
TXS_A
tus of the serial port channel's transmit buffer as follows: 11= buffer full,
00=buffer empty, 10=buffer partially full. These bits apply to multichan-
nel mode only.

Channel Selection Registers

Specific channels can be individually enabled or disabled to select the
words that are received and transmitted during multichannel communica-
tions. Data words from the enabled channels are received or transmitted,
while disabled channel words are ignored. Up to 128 channels are avail-
able for transmitting and receiving.
The multichannel selection registers enable and disable individual chan-
nels. The registers for each serial port are shown in
Table 9-2. Multichannel Selection Registers
Register Names
MR1CS(0–3)
MR3CS(0–3)
MR5CS(0–3)
MT0CS(0–3)
MT2CS(0–3)
MT4CS(0–3)
9-30
, Bit 29 (
SPCTL4
) in the ,
SPCTL0 SPCTL2
Function
Multichannel Receive Select specifies the active receive channels
(4x32-bit registers for 128 channels).
Multichannel Transmit Select specifies the active transmit channels
(4x32-bit registers for 128 channels).
ADSP-2126x SHARC Processor Hardware Reference
). The Transmit Underflow
TUVF_A
signal occurred.
SPORTx_FS
, registers indicate the sta-
SPCTL4
Table
TXS
9-2.