Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 702

I/O Processor Registers
SPMCTL01
(0xc04)
DMACHS1B
SPORT1 Channel B Status
DMA Chaining Status
DMACHS1A
SPORT1 Channel A Status
DMA Chaining Status
DMACHS0B
SPORT0 Channel B Status
DMA Chaining Status
DMACHS0A
SPORT0 Channel A Status
DMA Chaining Status
DMAS1B
SPORT1 Channel B Status/ DMA Status
DMAS1A
SPORT1 Channel A Status/DMA Status
15 14 13 12 11 10
Reserved
SPL
SPORT Loopback
SPORT0 A to SPORT1 A Only
SPORT0 B to SPORT1 B Only
NCH
Number of Channels – 1
Figure A-24. SPMCTL01 Register – Multichannel Mode
A-80
31 30 29 28 27 26 25
0 0 0 0 0 0 0
9 8
0 0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1
0 0 0 0 0 0 0
0
CHNL
Current Channel Status
(read-only)
MCEB
Multichannel Enable,
B Channels
1=Enable
0=Disable
DMAS0A
SPORT0 Channel A Status
DMA Status
DMAS0B
SPORT0 Channel B Status
DMA Status
0
0
MCEA
Multichannel Enable,
A Channels
1=Enable
0=Disable
MFDx
Multichannel Frame Delay