Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 451

When enabled as a master, the DMA engine transmits or receives data as
follows:
1. If the SPI system is configured for transmitting, the DMA engine
reads data from memory into the SPI DMA FIFO. Data from the
DMA FIFO is loaded into the
Transmit Shift register. This initiates the transfer on the SPI port.
2. If configured to receive, data from
into the SPI DMA FIFO, the DMA engine reads data from the SPI
DMA FIFO and writes to memory. Finally, the SPI initiates the
receive transfer.
3. The SPI generates the programmed signal pulses on
simultaneously shifts data out of
4. The SPI continues sending or receiving words until the SPI DMA
word count register transitions from 1 to 0.
If the DMA engine is unable to keep up with the transmit stream during a
transmit operation because the IOP requires the IOD (I/O data) bus to
service another DMA channel (or for another reason), the
until data is written into the
ation should be ignored. The data in the
be used, and the
bits (bits 26 and 29) should be ignored. The
SPISTAT
tion cannot generate an error interrupt in this mode.
If the DMA engine cannot keep up with the receive data stream during
receive operations, then
performing a receive DMA, the processor core assumes the transmit buffer
is empty. If
SENDZ
ADSP-2126x SHARC Processor Hardware Reference
TXSPI
(bits 28–27 and 31–30 in the
RXS
stalls until data is read from
SPICLK
= 1, the device repeatedly transmits 0's on the
Serial Peripheral Interface Port
register and then into the
TXSPI
is automatically loaded
RXSPI
and shifts data in from
MOSI
register. All aspects of SPI receive oper-
register is not intended to
RXSPI
SPCTLx
and
SPICLK
MISO
stalls
SPICLK
register) and
overrun condi-
ROVF
. While
RXSPI
pin.
MOSI
10-15
.