Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 175

Table 3-24 and
gram sequencer. All registers in the program sequencer are universal
registers (
Uregs
data memory. All of the sequencer's registers and the top of stacks are
readable and writable, except for the fetch address, decode address, and
PC. Pushing or popping the PC stack is done with a write to the PC stack
pointer, which is readable and writable. Pushing or popping the loop
address stack requires explicit instructions.
A set of system control registers configures or provides input to the
sequencer. These registers appear across the top and within the interrupt
controller and are shown in
instruction permits setting, clearing, toggling, or testing specific bits in
the system registers. For information on this instruction (Bit), see SHARC
Processor Programming Reference. Writes to some of these registers do not
take effect on the next cycle. For example, after a write to the
ter enables ALU saturation mode, the change takes effect two cycles after
the write. Also, some of these registers do not update on the cycle immedi-
ately following a write. An extra cycle is required before a register read
returns the new value.
With the lists of sequencer and system registers,
Table 3-25 summarize the number of extra cycles (latency) for a write to
take effect (effect latency) and for a new value to appear in the register
(read latency). A "0" indicates that the write takes effect or appears in the
register on the next cycle after the write instruction is executed, and a "1"
indicates one extra cycle.
ADSP-2126x SHARC Processor Hardware Reference
Table 3-25 list the registers within and related to the pro-
), so they are accessible to other universal registers and to
Figure 3-1 on page
Program Sequencer
3-3. A bit manipulation
MODE1
Table 3-24 and
regis-
3-63