Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 395

ADSP-21xxx DSP Development Software. All control and status bits in
the SPORT registers are active high unless otherwise noted.
Since the SPORT registers are memory-mapped, they cannot be written
with data directly from memory. Instead, they must be written from (or
read into) processor core registers, usually one of the general-purpose Uni-
versal registers (
Universal Status registers (
can also be written or read by external devices (for example, another pro-
cessor or a host processor) to set up a serial port DMA operation.
Table 9-5 provides a complete list of the SPORT registers in IOP address
order, showing the memory-mapped IOP address and a brief description
of each register.
Table 9-5. SPORT Registers
IOP Register
Address
0x400 SPCTL2
0x401 SPCTL3
0x402 DIV2
0x403 DIV3
0x404 SPMCTL23
0x405 MT2CS0
0x406 MT2CS1
0x407 MT2CS2
0x408 MT2CS3
ADSP-2126x SHARC Processor Hardware Reference
) of the register file or one of the general-purpose
R0–R15
USTAT1–USTAT4
Reset Description
0x0000 0000 SPORT2 Serial Control Register
0x0000 0000 SPORT3 Serial Control Register
None SPORT2 Divisor for Transmit/Receive SPORT2_-
CLK and SPORT2_FS
None SPORT3 Divisor for Transmit/Receive SPORT3_-
CLK and SPORT3_FS
None SPORT 2/3 Multichannel Control Register
None SPORT2 Multichannel Transmit Select 0
(Channel 31-0)
None SPORT2 Multichannel Transmit Select 1
(Channel 63-32)
None SPORT2 Multichannel Transmit Select 2
(Channel 95–64)
None SPORT2 Multichannel Transmit Select 3
(Channel 127–96)
). The SPORT control registers
Serial Ports
9-45