Dual Compute Units Sets - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

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Dual Compute Units Sets

The computational units (ALU, multiplier, and shifter) in PEx and PEy

are identical. The data bus connections for the dual computational units

permit asymmetric data moves to, from, and between the two processing

elements. Identical instructions execute on the PEx and PEy computa-

tional units; the difference is the data. The data registers for PEy

operations are identified (implicitly) from the PEx registers in the instruc-

tion. This implicit relationship between PEx and PEy data registers

corresponds to complementary register pairs in

) that do not appear in

in both PEx and PEy. When a computation in SIMD mode refers to a reg-

ister in the PEx column, the corresponding computation in PEy refers to

the complimentary register in the PEy column.

Table 2-15. SIMD Mode Complementary Register Pairs

ADSP-2126x SHARC Processor Hardware Reference

Processing Elements

2-15. Any universal

have the same identities

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