Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 682

Core Registers
Table A-20. EEMUSTAT Register Bit Descriptions (Cont'd)
Bit Name
3 STATIA0
4 STATIA1
5 STATIA2
6 STATIA3
7 STATIO0
8 Reserved
9 EEMUOUTIRQEN
10 EEMUOUTRDY
11 EEMUOUTFULL
12 EEMUINFULL
A-60
Description
Instruction Address Breakpoint Hit.
0 = No instruction address #0 breakpoint occurs
1 = Instruction address #0 breakpoint occurs
Instruction Address Breakpoint Hit.
0 = No instruction address #1 breakpoint occurs
1 = Instruction address #1 breakpoint occurs
Instruction Address Breakpoint Hit.
0 = No instruction address #2 breakpoint occurs
1 = Instruction address #2 breakpoint occurs
Instruction Address Breakpoint Hit.
0 = No instruction address #3 breakpoint occurs
1 = Instruction address #3 breakpoint occurs
DMA Peripheral Address Breakpoint Status.
breakpoint hit detected on the IOD/IOD0 bus
0 = No DMA peripheral address breakpoint occurs
1 = DMA peripheral address breakpoint occurs
Enhanced Emulation EEMUOUT Interrupt Enable.
0 = EEMUOUT interrupt disable
1 = EEMUOUT interrupt enable
Note: Interrupts are of the low priority variety
Enhanced Emulation EEMUOUT Ready.
1 = EEMUOUT FIFO contains valid data
0 = EEMUOUT FIFO is empty
Enhanced Emulation EEMUOUT FIFO Status.
0 = EEMUOUT FIFO is not full
1 = EEMUOUT FIFO full
Enhanced Emulation EEMUIN Register Status.
0 = EEMUIN register is empty
1 = EEMUIN register full
ADSP-2126x SHARC Processor Hardware Reference
1
1
1
1
1
Set bit if
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