Boundary Scan - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Boundary Scan

A Boundary Scan Description language (BSDL) file for the ADSP-2126x
is available on the Analog Devices Web site.
Refer to the IEEE 1149.1 JTAG specification for detailed information on
the JTAG interface. This chapter assumes a working knowledge of the
JTAG specification.
Boundary Scan
A boundary scan allows a system designer to test interconnections on a
printed circuit board with minimal test-specific hardware. The scan is
made possible by the ability to control and monitor each input and output
pin on each chip through a set of serially scannable latches. Each input
and output is connected to a latch, and the latches are connected as a long
Shift register so that data can be read from or written to them through a
serial test access port (TAP). The ADSP-2126x contains a test access port
compatible with the industry-standard IEEE 1149.1 (JTAG) specification.
Only the IEEE 1149.1 features specific to the ADSP-2126x are described
here. For more information, see the IEEE 1149.1 specification and the
other documents listed in
The boundary scan allows a variety of functions to be performed on each
input and output signal of the ADSP-2126x. Each input has a latch that
monitors the value of the incoming signal and can also drive data into the
chip in place of the incoming value. Similarly, each output has a latch that
monitors the outgoing signal and can also drive the output in place of the
outgoing value. For bidirectional pins, the combination of input and out-
put functions is available.
Every latch associated with a pin is part of a single serial shift register path.
Each latch is a master/slave type latch with the controlling clock provided
externally. This clock (
clock ( ).
CLKIN
6-2
"References" on page
) is asynchronous to the ADSP-2126x system
TCK
ADSP-2126x SHARC Processor Hardware Reference
6-9.