Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 619

Table 15-9. SPI Slave Boot Bit Settings
Bit Setting
SPIEN Set (= 1)
SPIMS Cleared (= 0)
MSBF Cleared (= 0)
WL 10, 32-bit SPI
DMISO Set (= 1) MISO
SENDZ Cleared (= 0)
SPIRCV Set (= 1)
CLKPL Set (= 1)
CPHASE Set (= 1)
The SPI DMA channel is used when downloading the boot kernel infor-
mation to the processor. At reset, the DMA Parameter registers are
initialized to the values listed in
Table 15-10. Parameter Initialization Value for Slave Boot
Parameter Register
SPICTL
SPIDMAC
IISPI
IMSPI
CSPI
ADSP-2126x SHARC Processor Hardware Reference
Comment
SPI enabled
Slave device
LSB first
Receive Shift register word length
MISO disabled
Send last word
Receive DMA enabled
Active low SPI clock
Toggle SPICLK at the beginning of the first bit
Table
Initialization Value
0x0000 4D22
0x0000 0007
0x0008 0000
0x0000 0001
0x0000 0180
System Design
15-10.
Comment
Enabled, RX, initialized on completion
Start of Block 0 NW memory
32-bit data transfers
15-29