Known Duration Accesses - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

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Using the Parallel Port

external byte address indicated by

fetched only when the core reads (empties)

The following are guidelines that programs must follow when the proces-

sor core accesses parallel port registers.

• While a DMA transfer is active, the core may only write the

isters or other bits in

parallel port to malfunction.

• Core reads of the FIFO register during a DMA operation are

allowed but do not affect the status of the FIFO.

DMA-driven), the current external bus cycle (

cycle) will complete but no further external bus cycles occur. Dis-

abling the parallel port clears the data in the

• Core reads and writes to the

tus of the FIFO when DMA is not active. This happens even when

the parallel port is disabled.

programs write to this register in cycle N, the new settings will not

be in effect until cycle N + 2. Avoid sampling

cycles after the

• For core-driven transfers over the parallel port, the

ters need to be initialized before accessing the

Known Duration Accesses

Of these methods, known duration accesses are the most efficient because

they allow the core to execute code while the transfer to/from the

. Accessing any of the DMA parameter reg-

is cleared while a transfer is underway (whether core or

registers are not used. Only the

ADSP-2126x SHARC Processor Hardware Reference

. Subsequently, additional data is

during an active transfer will cause the

registers update the sta-

cycle or data

until at least 2