Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 332

occurs in two cycles. In cycle one, the processor performs an
driving the 16 bits of external address,
port bus (pins
the second cycle, the processor either drives or receives the 16 bits of
external data (
This pattern repeats until the transfer completes.
However, a special case occurs when the external address modifier is zero,
( = 0). In this case, the external address is latched only once, using the
EMPP
cycle before the first data transfer. After the address has been latched
ALE
externally, the processor continues receiving and sending 16-bit data on
until the transfer completes. This mode can be used with external
AD15–0
FIFOs and high speed A/D and D/A converters and offers the maximum
throughput available on the parallel port (132 Mbyte/sec).
Figure 8-3 shows the connection diagram in 16-bit mode.
ADSP-2126x
Figure 8-3. External Transfer—16-bit Mode
8-10
), allowing the external latch to hold this address. In
AD15–0
) through the 16-bit parallel port bus (pins
ED15–0
AD[15-0]
16
ALE
ALE
RD
WR
SRAMCE
ADSP-2126x SHARC Processor Hardware Reference
, onto the 16-bit parallel
EA15–0
16
180
16
DATA[17-0]
68
LATCH
Q[15-0]
ADDR[23-8]
RD
WR
CE
FLASHCE
cycle,
ALE
AD15–0
FLASH
DATA[7-0]
SRAM
CE
).