Internal Memory; Dsp Architecture - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Internal Memory

Internal Memory
The ADSP-21262 and ADSP-21266 SHARC DSPs contain 2M bits of
internal RAM and 4M bits of internal ROM. Block 0 has 1M bit RAM
and 2M bits ROM. Block 1 has 1M bit RAM and 2M bits ROM.
Table 5-1 shows the maximum number of data or instruction words that
can fit in each internal memory block.

The ADSP-2126x family members are available with varying
amounts of internal ROM and RAM. For a complete list, visit our
web site at www.analog.com\SHARC.
Table 5-1. Words Per Internal Memory Block (ADSP-21262/21266
Models)
Word Type Bits Per
Word
Instruction 48 bits
Long Word 64 bits
Data
Extended- 40 bits
Precision
Normal Word
Data
Normal Word 32 bits
Data
Short Word 16 bits
Data

DSP Architecture

Most microprocessors use a single address and a single-data bus for mem-
ory accesses. This type of memory architecture is referred to as the Von
Neumann architecture. Because DSPs require greater data throughput
5-2
Maximum Number of Words in
Block 0
1M bit RAM 2M bits ROM
21.33K words 42K words
16K words 32K words
21.33K words 42K words
32K words 64K words
64K words 128K words
ADSP-2126x SHARC Processor Hardware Reference
Maximum Number of Words in
Block 1
1M bit RAM 2M bits ROM
21.33K words 42K words
16K words 32K words
21.33K words 42K words
32K words 64K words
64K words 128K words