Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 568

PCG Programming Examples
/* Enable DAI Pins 1 & 2 as outputs */
r0 = PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PB02);
dm(SRU_PBEN0) = r0;
r0 = (100<<PCG_PWB);
dm(PCG_PW) = r0;
r2 = 1000; /* Define 20-bit Phase Shift */
r0 = (ENFSB|ENCLKB|
1000000);
r1 = lshift r2 by -10;
/* Deposit the upper 10-bits of the Phase Shift in the */
/* correct position in PCG_CTLB0 (Bits 20-29) */
r1 = fdep r1 by 20:10;
r0 = r0 or r1;
dm(PCG_CTLB1) = r0;
dm(PCG_CTLB0) = r0;
r0 = (100000);
/* Deposit the lower 10-bits of the Phase Shift in the */
/* correct position in PCG_CTLB1 (Bits 20-29) */
r1 = fdep r2 by 20:10;
r0 = r0 or r1;
dm(PCG_CTLB1) = r0;
//----------------------------------------
_main.end: jump(pc,0);
Listing 13-2. PCG Channel A and B Output Example
/* Register Definitions */
#define SRU_CLK3
13-14
/* PCG Channel B FS Pulse width = 100 */
/*Enable PCG Channel B Clock and FS*/
/* FS Divisor = 1000000 */
/* Phase Shift 10-19 = 0 */
/* Clk Divisor = 100000 */
/* Use CLKIN as clock source */
/* Phase Shift 10-19 = 0x3E8 */
0x2434
ADSP-2126x SHARC Processor Hardware Reference