Optimizing Cache Usage - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

cache hit. The same instruction does generate a hit and can be taken from
the cache after the cache is enabled.
If the cache freeze bit of the
data access instruction n, then the n+2 instruction is cached. This results
from the effect latency of the

When a program changes the cache mode, an instruction contain-
ing a program memory data access must not be placed directly after
a cache enable or cache disable instruction. This is because the DSP
must wait at least one cycle before executing the PM data access. A
program should have a
inserted after the cache enable instruction.

Optimizing Cache Usage

Cache operation is usually efficient and requires no intervention. How-
ever, certain ordering of instructions can work against the cache's
architecture, reducing its efficiency. When the order of PM data accesses
and instruction fetches continuously displaces cache entries and loads new
entries, the cache does not operate efficiently. Rearranging the order of
these instructions remedies this inefficiency. Optionally, a dummy PM
read can be inserted to trigger the cache.
When a cache miss occurs, the needed instruction is loaded into the cache
so that if the same instruction is needed again, it will be there (that is, a
cache hit will occur). However, if another instruction whose address is
mapped to the same set displaces this instruction, a cache miss occurs. The
bits help to reduce this possibility since at least two other instructions,
LRU
mapped to the same set, are needed before an instruction is displaced. If
three instructions mapped to the same set are all needed repeatedly, cache
efficiency (that is, "hit rate") can go to zero. To solve this problem, move
one or more instructions to a new address that is mapped to a different
cache set.
ADSP-2126x SHARC Processor Hardware Reference
register is set by a program memory
MODE2
register.
MODE2
or other non-conflicting instruction
NOP
Program Sequencer
3-9