Using The Cache - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Instruction Cache
are made to the same block in internal memory. This scenario occurs
when data is accessed from the same block from which the instructions are
executed. This scenario also occurs when an instruction performs both a
DM and PM access to the same block in one instruction. In the first case,
the instruction takes two cycles to complete, with the data being accessed
in the first cycle and the instruction in the second. In the latter case, where
a dual data access is performed, the processor takes three cycles to com-
plete the instruction.

Block conflicts are not cached.

Using the Cache

After a DSP reset, the cache is cleared (it contains no instructions), unfro-
zen, and enabled. From then on, the
mode of the instruction cache as shown below.
• Cache Disable. Bit 4 (
cache (if 1) or enable the cache (if 0).
• Cache Freeze. Bit 19 (
contents of the cache (if 1) or let new entries displace the entries in
the cache (if 0).
Table A-3 on page A-8
Freezing the cache prevents any changes to its contents—a cache miss does
not result in a new instruction being stored in the cache. Disabling the
cache stops its operation completely; all instruction fetches conflicting
with program memory data accesses are delayed by the access. These func-
tions are selected by the
freeze) bits in the
The cache content stays valid when the cache is disabled. The effect of dis-
abling the cache is that an already cached instruction does not generate a
3-8
) directs the sequencer to disable the
CADIS
) directs the sequencer to freeze the
CAFRZ
lists all the bits in the
(cache enable/disable) and
CADIS
register.
MODE2
ADSP-2126x SHARC Processor Hardware Reference
register controls the operating
MODE2
register.
MODE2
(cache
CAFRZ