Loops And Sequencing - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

• TCB loading takes 16 core clock cycles to configure 4 IOP regis-
ters. This access is not divisible.

Loops and Sequencing

Another type of nonsequential program flow that the sequencer supports
is looping. A loop occurs when a
repeat a sequence of instructions until a condition tests true. Unlike other
processors, the SHARC automatically evaluates the loop termination con-
dition and modifies the Program Counter (
allows zero overhead looping.
In addition to the standard status flags available to all conditional instruc-
tions ( , ,
EQ GT LT
Expired ( ), is specifically used for terminating loops. This instruction
LCE
tests whether the loop has completed the required number of iterations in
the register. Loops that terminate with conditions other than
LCNTR
have some additional restrictions. For more information, see
on Ending Loops" on page 3-27
page 3-28. For more information on condition types in
tions, see "Interrupts and Sequencing" on page

The DSP's SIMD mode influences the execution of loops.
The / instruction uses the sequencer's loop and condition features,
DO UNTIL
as shown in Figure 3-1 on page
ware loops without the overhead of additional instructions to branch, test
a condition, or decrement a counter. The following code example shows a
/ loop that contains three instructions and iterates 30 times.
DO UNTIL
LCNTR = 30, DO the_end UNTIL LCE; /*Loop iterates 30 times*/
R0 = DM(I0,M0), F2 = PM(I8,M8);
R1 = R0-R15;
the_end: F4 = F2 + F3;
ADSP-2126x SHARC Processor Hardware Reference
DO
, and so on), a special condition instruction Loop Counter
and
3-3. These features provide efficient hard-
Program Sequencer
/ instruction causes the DSP to
UNTIL
) register appropriately. This
PC
"Restrictions on Short Loops" on
3-48.
/*Last instruction in loop*/
LCE
"Restrictions
/ instruc-
DO UNTIL
3-25