Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 341

and . For all four of these methods, the core uses the same basic steps
PPTX
to initiate the transfer. However, each method uses a different technique
to complete it. The following steps provide the basic procedure for setting
up and initiating a data transfer using the core.
1. Write the external byte address to the
address modifier to the
Before initializing or modifying any of the parallel port parameter
registers such as
abled (bit 0,
when
PPEN
re-enabled. This sequence is most often used to perform
non-sequential, external transfers, such as when accessing taps in a
delay line.
For core-driven transfers, the
used. Although these registers are automatically updated by the
parallel port (the
be left uninitialized without consequence.
2. Initialize the
These include the parallel port data-cycle duration (
whether the transfer is a receive or transmit operation (
core-driven transfers, be sure to clear the DMA enable bit,
In this same write to
bit 0,
PPEN
When enabling the parallel port (setting
ity varies, depending on the direction of data transfer (receive or
transmit). For transmit operations (
perform any external accesses until valid data is written to the
by the core.
For read operations (
(=1), the parallel port immediately fetches two 32-bit data words from the
ADSP-2126x SHARC Processor Hardware Reference
EMPP
and
EIPP EMPP
, of the
PPEN PPCTL
=0, can those registers be modified and the port then
register decrements for example), they may
ECPP
register with the appropriate settings.
PPCTL
, the port may also be enabled by setting
PPCTL
, to 1.
PPTRAN
= 0), two core clock cycles after
PPTRAN
register and the external
EIPP
register.
, the parallel port must first be dis-
register must be cleared). Only
, , , and
ECPP IIPP IMPP
= 1), the external bus activ-
PPEN
= 1), the parallel port does not
Parallel Port
are not
ICPP
) and
PPDUR
). For
PPTRAN
.
PPDEN
register
TXPP
is set
PPEN
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