Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 700

I/O Processor Registers
Table A-23. SPCTLx Register Bit Descriptions (Cont'd)
Bits Name
22 FS_BOTH
23 BHD
24 SPEN_B
25 SPTRAN
26 ROVF_B,
TUVF_B
28–27 DXS_B
29 ROVF_A or
TUVF_A
31–30 RXS_A or
TXS_A
A-78
Definition
FS Both Enable. This bit issues WS if data is present in both trans-
mit buffers, if set (= 1). If cleared (= 0), WS is issued if data is pres-
ent in either transmit buffer. This bit is reserved when the SPORT is
2
in multichannel, I S and Left-justified Sample Pair mode.
Buffer Hang Disable. This bit ignores a core hang, when set (= 1).
When cleared (= 0), this bit indicates a core stall. The core stall
occurs when the transmit buffer is full or the receive buffer is empty
and the core tries to write or read from the FIFO respectively. This
bit applies to all modes
Enable Channel B Serial Port. Enables if set, (= 1) or disables if
cleared, (= 0) the corresponding serial port B channel.
This bit is reserved when the SPORT is in Multichannel mode.
Data Direction Control. Enables receive buffers if cleared (= 0), or
activates transmit buffers if set (= 1). This bit is reserved when the
SPORT is in Multichannel mode.
Channel B Error Status (sticky, read-only). Indicates if the serial
transmit operation has underflowed or a receive operation has over-
flowed in the channel B data buffer. This bit is reserved when the
SPORT is in Multichannel mode.
Channel B Data Buffer Status (read-only). Indicates the status of
the serial port's channel B data buffer as follows: 11 = full, 00 =
empty, 10 = partially full. This bit is reserved when the SPORT is in
Multichannel mode.
Channel A Error Status (sticky, read-only). Indicates if the serial
transmit operation has underflowed or a receive operation has over-
flowed in the channel A data buffer.
Channel A Data Buffer Status (read-only). Indicates the status of
the serial port's channel A data buffer as follows: 11 = full, 00 =
empty,
10 = partially full.
ADSP-2126x SHARC Processor Hardware Reference