Table of Contents
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I/O Processor Registers
SRU_FS1 (0x2452)
Reserved
IDP2_FS_I
Input Data Port 2 Frame Sync Input
15 14 13 12 11 10
0
Figure A-44. SRU_FS1 Register
SRU_FS2 (0x2453)
Reserved
IDP7_FS_I
Input Data Port 7 Frame Sync Input
15 14 13 12 11 10
0
IDP5_FS_I
Input Data Port 5 Frame Sync Input
IDP4_FS_I
Input Data Port 4 Frame Sync Input
Figure A-45. SRU_FS2 Register
Table A-36. Group C Sources – Frame Sync
Selection Code
00000 (0x0)
00001 (0x1)
00010 (0x2)
A-124
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
1
1
1
1
0
1
9
8
1
1
1
1
0
1
1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
1
1
1
1
0
1
9
8
1
1
1
1
0
1
1
Source Signal
DAI_PB01_O
DAI_PB02_O
DAI_PB03_O
ADSP-2126x SHARC Processor Hardware Reference
1
1
1
0
1
1
1
7
6
5
4
3
2
1
0
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
7
6
5
4
3
2
1
0
1
1
0
1
1
1
1
0
Description
Select DAI Pin Buffer 1 as the source
Select DAI Pin Buffer 2 as the source
Select DAI Pin Buffer 3 as the source
1
IDP0_FS_I
Input Data Port 0
Frame Sync Input
IDP1_FS_I
Input Data Port 1
Frame Sync Input
Reserved
1
IDP6_FS_I
Input Data Port 6
Frame Sync Input
IDP3_FS_I
Input Data Port 3
Frame Sync Input
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