Phase-Locked Loop Startup - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

If the pin is not asserted (or held low) at power-up, the JTAG port is
TRST
in an undefined state that may cause the processor to drive out on I/O
pins that would normally be three-stated at reset. The
held low with a jumper to ground on the target board connector.
A detailed discussion of JTAG and its use can be found in the Engi-
neer-to-Engineer Note (EE-68), Analog Devices JTAG Emulation Technical
Reference. This document is available on the Analog Devices Web site at
www.analog.com.

Phase-Locked Loop Startup

The signal can be held low long enough to guarantee a stable
RESET
source and stable
RESET
CLKIN
Figure 15-3. Chip Reset Circuit
In order for the PLL to lock to the
lock before the core can execute or begin the boot process. A delayed core
reset has been added via the delay circuit. There is a 12-bit counter that
ADSP-2126x SHARC Processor Hardware Reference
/ power supplies before the PLL is reset.
VDDINT VDDEXT
Core Reset Delay Circuit
ENA_CNT
CORE_RST
CLKIN
12-bit Counter
Count 4096 CLKIN Cycles
CLKIN
System Design
TRST
PLL reset and PLL clock
input enable occur on the
rising edge of RESET
PLL_RESET
ENA_CLK
CLKIN
Delayed Internal
Core Processor
Reset
RESETOUT
frequency, the PLL needs time to
pin can be
CLKIN
PLL
15-13