Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 811

I INDEX
Numerics
16-bit floating-point format,
16-bit mode, 8-9, 8-11,
16-bit to 32-bit word packing enable
(PACK), 9-54
32-bit data, normal word,
32-bit shift registers,
32-bit single-precision floating-point
format, 2-5
40-bit extended precision,
40-bit extended-precision floating-point
format, 2-6
64-bit signed fixed-point product,
8-bit mode, 8-9, 8-11,
A
ABS function, 2-17
absolute address, 3-12,
AC (ALU fixed-point carry) bit,
AC bit, 2-19, 3-19
access to SPI registers,
A channel See TXSP5A register
active edge, defined, 10-5
active low versus active high frame syncs,
9-36
active state multichannel receive frame sync
select See LMFS bit
AD1855 stereo DAC, power down,
ADD instruction, 2-17,
address
latch enable See also ALE pin
ADSP-2126x SHARC Processor Hardware Reference
2-7
8-14
5-26
A-100
1-3
2-9
8-14
G-3
A-12
10-34
10-7
2-44
address bus, 1-2
address fields, A-33
address generator, 7-26
addressing
even short words, 5-31
odd short words, 5-31
See post-modify, modify, bit-reverse, or
circular buffer
storing top-of-loop addresses, 3-16,
with DAGs, 4-10
ADSP-2126x processor
configured as slave device,
design advantages,
enhancements, 1-14
processor core, 1-5
AF (ALU floating point operation) bit,
A-14
AF bit, 2-19
AI (ALU floating-point invalid operation)
bit, A-13
AI bit, 2-19
AIS (ALU floating-point invalid) bit,
AIS bit, 2-19
A-law companding See companding
(compressing/expanding)
ALE
cycle, 8-5
pin, 8-3
aligning data, 5-13
alternate DAG registers,
alternate registers See also secondary
registers, 1-8
A-33
10-6
1-1
A-18
4-6
I-1