Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 613

to 32 bits. Therefore, for 8 or 16-bit devices, data words are packed into
the Shift register to generate 32-bit words least significant bit (LSB) first,
which are then shifted into internal memory. The relationship between
the 32-bit words received into the
need to be placed in internal memory is shown in
For more information about 32- and 48-bit internal memory addressing,
see "Setting Data Access Modes" on page
32-BIT RECEIVE
SHIFT
REGISTER
S
P
I
R
X
MOSI
Figure 15-7. SPI Data Packing
For 16-bit SPI devices, two words shift into the 32-bit receive Shift regis-
ter ( ) before a DMA transfer to internal memory occurs. For 8-bit SPI
RXSR
devices, four words shift into the 32-bit receive shift register before a
DMA transfer to internal memory occurs.
When booting, the ADSP-2126x processor expects to receive words into
the register seamlessly. This means that bits are received continu-
RXSPI
ously without breaks.
Receive Operations" on page 10-12.
ADSP-2126x SHARC Processor Hardware Reference
RXSPI
#384:DM[0X8017F]
MSW
DMA #6: DM[80005]
MSW
DMA
DMA #4: DM[80003]
MSW
PM48 [0X80002]
DMA #2: DM[80001]
MSW
[X80001]
4
16
For more information, see "Core Transmit and
For different SPI host sizes, the
System Design
register and the instructions that
Figure 15-7.
5-27.
#384:DM[0X8017E]
LSW MSW LSW
PM48 [0X800FF]
DMA #5: DM[80004]
LSW MSW
PM48 [0X80003]
DMA #3: DM[40002]
LSW MSW
PM48 [0X80001]
DMA #1: DM[80000]
LSW MSW
UW PM48 [0X80000]
3 2
0X800FF
[X800FE]
LSW
[X80002]
256 48-BIT
WORDS
LSW
LSW
LW
0X80000
1
15-23